Chip designer Mr. Bubble: AI hashrate bottlenecks have shifted to advanced packaging, interconnect latency, and memory hierarchies; Moore's Law economics are broken.

Senior chip designer Mr. Bubble stated in a podcast interview that the true bottleneck for AI computing infrastructure is no longer the chips themselves, but rather more fundamental issues such as packaging, interconnect latency, and storage hierarchy. He emphasized that the economic logic of Moore's Law has broken, with the cost of increasing transistor density being high and yielding diminishing returns, making advanced packaging the new key. Mr. Bubble cited NVIDIA's Rubin Ultra architecture as an example, revealing that its roadmap is constrained by memory and packaging supply chains, with PCB manufacturers even becoming a new bottleneck. He believes that the future design focus for AI computing will be the "entire rack," where interconnect throughput and latency are crucial, and predicts that 3D DRAM will be the ultimate form of memory. Mr. Bubble also questioned the true motives behind large model labs' "pushing boundaries" narrative and suggested that investors should focus on underlying hardware and supply chains rather than competing frontier AI labs.